The present invention relates generally to planar lightwave circuits. More particularly, the present invention relates to a method and system for performing deep trench etching in a planar lightwave circuit for stress relief and thermal isolation, and other applications.
Planar lightwave circuits comprise fundamental building blocks for the newly emerging, modern fiberoptic communications infrastructure. Planar lightwave circuits are innovative devices configured to transmit light in a manner analogous to the transmission of electrical currents in printed circuit boards and integrated circuit devices. Examples include arrayed waveguide grating devices, integrated wavelength multiplexers/demultiplexers, optical switches, optical modulators, wavelength-independent optical couplers, and the like.
Planar lightwave circuits (PLCs) generally involve the provisioning of a series of embedded optical waveguides upon a semiconductor substrate (e.g., silicon). PLCs are constructed using the advanced tools and technologies developed by the semiconductor industry. Modern semiconductor electronics fabrication technology can aggressively address the increasing need for integration and is currently being used to make planar lightwave circuits. By using manufacturing techniques closely related to those employed for silicon integrated circuits, a variety of optical elements can be placed and interconnected on the surface of a silicon wafer or similar substrate. This technology has only recently emerged and is advancing rapidly with leverage from the more mature tools of the semiconductor-processing industry.
A conventional PLC optical waveguide comprises a substrate (e.g., silicon) with a un-doped silica glass bottom clad formed thereon, at least one waveguide core formed on the bottom clad, and a top clad covering the waveguide core and the bottom clad, wherein a certain amount of at least one dopant is added to the waveguide core so that the refractive index of the waveguide core is higher than that of the top clad and bottom clad. The waveguide cores are formed by etching their profile from a core layer (e.g., doped SiO2 glass) deposited over the bottom clad. The core layer is patterned by, for example, reactive-ion etching to remove the excess doped SiO2 glass, and thereby define the profile of one or more waveguide cores. An SiO2 top clad layer is then formed (e.g., by flame deposition or PECVD). The optical waveguide is subsequently heated to a certain temperature to stabilize the refractive index of the top clad and to make the top clad more homogenous. Finally, the wafer is diced into multiple PLC dies and packaged according to their particular applications.
A well-known problem with many planar lightwave circuits is the polarization sensitivity of the devices. Polarization sensitivity is a problem for both active PLC devices and passive PLC devices. For example, with many PLC devices, such as arrayed waveguide grating (AWG) devices, Mach-Zehnder thermo-optic devices, and the like, the switching/routing components of the devices must be substantially polarization insensitive. However, the presence of stress within the silica layers and the substrates of the devices causes different propagation constants for TE (transverse electric) and TM (transverse magnetic) propagation modes, typically referred to as birefringence. Birefringence and polarization sensitivity tends to be more problematic with active PLC devices, particularly thermo-optic PLC devices, where thermally induced birefringence exists in addition to any xe2x80x9cintrinsicxe2x80x9d birefringence of the PLC waveguides.
There exists an additional problem, with respect to thermal isolation. In active thermo-optic PLC devices, heat applied to one waveguide core needs to be thermally isolated from adjacent waveguide cores within the same device. Thermo-optic devices rely upon the selective heating of the silica waveguides to modulate the refractive index of the individual waveguides. This heat is used to precisely control the phase difference between light propagating along adjacent waveguides. Accordingly, one waveguide needs to be heated in a very controlled manner with respect to an adjacent waveguide. Unfortunately, due to the nature of transmission of thermal energy through the silica comprising the waveguides, thermal isolation between adjacent waveguides can be problematic.
An additional problem with active thermo-optic PLC devices is the fact that the heat used to modulate the phase of light propagating through the waveguides also induces stress (e.g., due to different coefficients of thermal expansion of the core, top clad, bottom clad, etc.) within the structure of the waveguides. This stress produces the different propagation constants for TE (transverse electric) and TM (transverse magnetic) propagation modes, and thus, the birefringence. This mismatch can cause a polarization dependent loss, wherein either the TE or TM mode is attenuated within the optical waveguide structures to a greater degree than the other, and other types of problems.
Thus, what is required is a solution that minimizes thermally induced birefringence within thermo-optic PLC devices. What is required is a solution that improves thermal isolation between adjacent waveguides of an active thermo-optic PLC device. Additionally, the required solution should be compatible with widely used PLC fabrication methods. The present invention provides a novel solution to the above requirements.
The present invention provides a solution that minimizes thermally induced dn/dt birefringence within thermal optic PLC devices. The present invention provides a solution that improves thermal isolation between adjacent thermal optic waveguides of an active PLC device. Additionally, the process of the present invention is compatible with widely used PLC fabrication methods.
In one embodiment, the present invention is implemented as a deep trench etching process for making an optical waveguide structure having improved thermal isolation and stress reduction. The method etches both deep trenches and shallow trenches in a single step. The method includes the step of depositing a partial top clad layer over a first and second waveguide core. An etch back is then performed on the partial top clad layer to obtain a desired thickness of the partial top clad layer. A first hard mask layer is subsequently deposited over the partial top clad layer. A set of hard masks are then formed over the first and second waveguide cores by patterning and etching the first hard mask layer. A full top clad layer is then deposited over the partial top clad layer and the set hard masks to form a top clad. A second hard mask layer is then deposited over the top clad. A deep trench area and first and second shallow trench areas are then exposed by patterning and etching the second hard mask layer. The deep trench area and the first and second shallow trench areas are then simultaneously etched to form a deep trench extending from the upper surface of the top clad to an underlying substrate, and first and second shallow trenches extending from the upper surface of the top clad to the set of hard masks. The set of hard masks and the second hard mask layer are then removed. Reactive ion etching can be used to etch the first and second hard mask layers. The hard mask layers can be amorphous silicon.
In another embodiment, the present invention is implemented as a deep trench etching process wherein a passivation layer is formed over a top clad of an optical waveguide structure of a planar lightwave circuit and a hard mask layer is subsequently deposited over the passivation layer. In this embodiment, a single deep trench is etched as opposed to simultaneously etching a shallow trench and a deep trench. A trench area of the top clad is exposed by patterning and etching the hard mask layer. The trench area of the top clad is subsequently etched to form a deep trench in the waveguide structure extending from the upper surface of the top clad to an underlying substrate. Amorphous silicon is used for the hard mask.
In both embodiments, a reactive ion etching process or a wet etching process can be used to etch the deep trench. Due to the much higher selectivity of Si with respect to SiO2, the hard mask layer protects adjacent areas of the top clad during the etch process. The hard mask is subsequently removed after etching the deep trench. The trench is disposed parallel to the optical core of the waveguide structure and is configured to both relieve stress and to thermally isolate the optical core. In this manner, the deep trench minimizes thermally induced dn/dt birefringence within thermal optic PLC devices and improves thermal isolation between adjacent thermal optic waveguides of an active PLC device. Both embodiments are compatible with widely used PLC fabrication methods.